Recently, as a display device, a liquid crystal display device (LCD), featured by a thin thickness, a light weight and low power dissipation, has come into extensive use, and is widely used for a display unit of mobile equipment, such as mobile phone, PDA (personal digital assistant) or a notebook PC (personal computer). However, the technique for enlarging the display size of the display device or coping with a moving picture has made progress, such that a stationary large-size display device or a large display size liquid crystal television receiver has now been offered to the market. As the liquid crystal display device, a liquid crystal display device of an active matrix driving system, capable of high definition display, is currently used.
FIG. 28 illustrates a liquid crystal display device. It is noted that FIG. 28 shows only an equivalent circuit of the main structure connected to a pixel of the display unit. Referring to FIG. 28, the liquid crystal display device of the active matrix driving system is briefly described. In general, a display unit 960 of a liquid crystal display device of the active matrix driving system is made up by a semiconductor substrate, a counter substrate, having a transparent electrode 966 formed on its entire surface, and a liquid crystal enclosed between the semiconductor substrate and the counter substrate. The semiconductor substrate carries plural transparent electrodes 964 and plural thin-film transistors (TFTs), arranged in a matrix configuration. In the case of, for example, a color SXGA panel, the display unit 960 is formed by 1280×3 pixel rows and 1024 pixel columns. For image display, the TFT 963, having a switching function, is controlled by a scanning signal, the grayscale voltage, corresponding to a video signal, is applied to the pixel electrode 964 when the TFT 963 is turned on, the transmittance of the liquid crystal is changed, based on the potential difference between the pixel electrode 964 and the counter substrate electrode(common electrode) 966, and the electric potential difference is maintained for a preset interval by a capacitance 965 of the liquid crystal. On the semiconductor substrate, a plurality of data lines 962 each supplying plural level voltages (grayscale voltage) to be applied to the pixel electrode 964, and a plurality of scanning lines 961 each supplying a scanning signal are interconnected in a lattice form. In the case of the aforementioned color SXGA panel, the there are provided 1280×3 data lines and 1024 scanning lines. The data line and the scanning line represent a significant capacitive load by the capacitance generated at the intersection and the capacitance of the liquid crystal sandwiched between the substrates. Meanwhile, the scanning signal is supplied by a gate driver 970 to the scanning line 961, while the grayscale voltage is supplied to each pixel electrode 964 via a data line 962 from the data driver 980. Re-writing of one frame data occurs every frame period ( 1/60 second) and each scanning line sequentially selects each pixel row, while each data line supplies the grayscale voltage during the selection period. It is noted that, while the gate driver 970 only has to supply at least binary-level scanning signals, while the data driver 980 has to drive the data line, as a large capacitive load, with the grayscale voltage of a high voltage accuracy, at a high speed. Hence, a differential amplifier of a high driving ability is preferentially used for the buffer unit of the data driver 980. For this differential amplifier, a rail-to-rail differential amplifier, in which the power supply voltage range is substantially coincident with the dynamic range (driving voltage range) is used for reducing the power dissipation (for example, see the Patent Publications 1 and 2 and the Non-Patent Publication 1).
A conventional rail-to-rail differential amplifier is hereinafter explained. FIG. 29 shows a differential amplifier disclosed in for example the following Patent Publication 1. The Patent publication 1 is referred to in the Patent publication 2. The differential amplifier, shown in FIG. 29, is introduced in detain in the Non-Patent publication 1. The differential amplifier, shown in FIG. 29, is now described briefly.
Referring to FIG. 29, this differential amplifier has a differential amplifying stage made up by an N-channel differential pair 711, 712, driven by a current source 710, a P channel differential pair 721, 722, driven by a current source 720, a cascode current mirror circuit 71, formed by vertical transistor pairs 713, 714 and 715, 716, a cascode current mirror circuit 72, formed by vertical transistor pairs 723, 724 and 725, 726, and floating current sources 73 and 74, formed by transistors 731, 732 and 741, 742. The differential amplifier includes an output amplifying stage formed by a push-pull stage constituted by transistors 101 and 102. VDD and VSS denote the high potential side power supply and the low potential side power supply, respectively. An output of the N-channel differential pair 711, 712 is supplied to a current mirror circuit 71 (connection nodes of the transistor pair 713, 714 and a transistor pair 715, 716), while an output of the P-channel differential pair 721, 722 is entered to a current mirror circuit 72 (connection nodes of the transistor pair 723, 724 and a transistor pair 725, 726). The current mirrors 71 and 72 are connected by floating current sources 73 and 74. The control terminal of the transistor 101 of the output amplifying stage is connected to a connection node (terminal 10) of the drain of the transistor 716 as the first differential output terminal and the floating current source 74, while the control terminal of the transistor 102 is connected to a connection node (terminal 20) of the drain of the transistor 726 as the first differential output terminal and the floating current source 74. The gates of the transistors 731, 732, 741 and 742, as the floating current sources, are supplied with bias voltages V1, V2, V3 and V4, respectively. The gates of the transistors 712 and 722 are connected to the input terminal 1 to form a non-inverting input terminal, while the gates of the transistors 711 and 721 are connected to the input terminal 2 to form an inverting input terminal. The non-inverting input terminal 1 and the inverting input terminal 2 are supplied with voltages VinP and VinN, respectively.
The operation of the differential amplifier, shown in FIG. 29, is explained. The differential amplifier is in a steady state when the voltage VinP of the non-inverting input terminal is equal to the voltage VinN of the inverting input terminal. In the steady state, the current flowing through the transistors of the differential transistor pair of the same polarity is equal. The two current paths flowing from the current mirror circuit 71 through the floating current sources 73 and 74 to the current mirror circuit 72 are controlled to be constant by the floating current sources 73 and 74, respectively.
If the voltage VinP of the non-inverting input terminal is higher than the voltage VinN of the inverting input terminal, the current flowing through the N-channel differential pair 711, 712 is such that the current flowing through the transistor 711 is decreased, while the current flowing through the transistor 712 is increased. As the current flowing through the transistor 711 is decreased, the current through the transistor 713 is decreased and, by the current mirror circuit 71, the current flowing through the transistors 714 and 716 is decreased. At this time, the floating current source 74 tends to cause the same current as the steady state current from the connection node with the transistor 716 (terminal 10) towards the connection node with the transistor 726. Thus, the gate voltage of the transistor 101 is pulled down, such that the charging current from the power supply VDD to the output terminal 3 is increased by the transistor 101. On the other hand, the current flowing through the P channel differential pair 721, 722 is such that, when the voltage VinP of the non-inverting input terminal is higher than the voltage VinN of the inverting input terminal, the current flowing through the transistor 721 is increased, while that flowing through the transistor 721 is decreased. With the current flowing through the transistor 721 increasing, the current through the transistor 723 is increased and, by the current mirror circuit 72, the current flowing through the transistors 724 and 726 is increased. At this time, the floating current source 74 tends to cause the same constant current as the steady state current to flow from the connection node with the transistor 716 towards the connection node with the transistor 726. Thus, the gate voltage of the transistor 102 is pulled down, such that the discharge current from the output terminal 3 to the power supply VSS is decreased by the transistor 102, and hence the output voltage Vout is increased.
When the voltage VinP of the non-inverting input terminal becomes lower than the voltage VinN of the inverting input terminal, the current flowing through the transistors of the N-channel differential pair 711, 712 is such that the current flowing through the transistor 711 is increased, while that flowing through the transistor 712 is decreased. With the current flowing through the transistor 711 increasing, the current through the transistor 713 is increased and, by the current mirror circuit 71, the current flowing through the transistors 714 and 716 is increased. At this time, the floating current source 74 tends to cause the same constant current as the steady state current to flow from the connection node with the transistor 716 towards the connection node with the transistor 726. Thus, the gate voltage of the transistor 101 is pulled up, such that the charging current from the power supply VDD to the output terminal 3 is decreased by the transistor 101. On the other hand, the current flowing through the P channel differential pair 721, 722 when the voltage VinP of the non-inverting input terminal is lower than the voltage VinN of the inverting input terminal is such that the current flowing through the transistor 721 is decreased, while that flowing through the transistor 722 is increased. With the current flowing through the transistor 721 decreasing, the current through the transistor 723 is also decreased and, by the current mirror circuit 72, the current flowing through the transistors 724 and 726 is decreased. At this time, the floating current source 74 tends to cause the same constant current as the steady state current to flow from the connection node with the transistor 716 towards the connection node with the transistor 726. Thus, the gate voltage of the transistor 102 is pulled up, such that the discharge current from the output terminal 3 to the power supply VSS is increased by the transistor 102, and hence the output voltage Vout is decreased.
In case the differential amplifier shown in FIG. 29 is used as a buffer unit of the data driver, the inverting input terminal 2 and the output terminal 3 are connected common in a voltage follower configuration. The grayscale voltage, corresponding to the video signal, is supplied to the non-inverting input terminal 1 of the differential amplifier. The grayscale voltage is subjected to current amplification and output at the output terminal 3 to drive the data line.
In the following Patent publication 2, the structure shown in FIG. 30 is proposed as a high slew rate differential amplifier employing the differential amplifier shown in FIG. 29. FIG. 30 depicts a differential amplifier designed to achieve high speed as the increase of the power dissipation is suppressed to the smallest value possible.
Referring to FIG. 30, the high slew rate differential amplifier circuit is featured by including subsidiary current source circuits 75, 76, in parallel with the current sources 710, 720 of the differential stage. The subsidiary current source circuit 75 includes a series connection of a current source 750 and a transistor 751. The gate of the transistor 751 is connected common to the gate of the transistor 102 of the push-pull output stage. The subsidiary current source circuit 76 includes a series connection of a current source 760 and a transistor 761. The gate of the transistor 761 is connected common to the gate of the transistor 101 of the push-pull output stage. Turning to the operation of the subsidiary current source circuits 75, 76, the gate voltages of the transistors 101 and 102 of the push-pull output stage are changed during the charging and discharging operations of the transistors 101 and 102 of the push-pull output stage. That is, the transistors 751 or 761 are turned on to increase the current flowing through the differential stage by an amount corresponding to that of the current sources 750 or 760. Thus, the current flowing through the differential stage is increased only at the time of the charging or discharging operations, as the current consumption under the steady state with the constant output is suppressed, thereby enabling the high speed operation.
[Patent Document 1]
    Japanese Patent Kokai Publication No. JP-A-6-326529 (FIG. 1)[Patent Document 2]    Japanese Patent Kokai Publication No. JP-P2001-156559A (FIG. 1)[Non-Patent Document 1]    ‘Analog/Digital Hybrid System LSI (low voltage low power dissipation circuit technology)’, Baihuukan, pp. 253